The present invention relates to an apparatus for converting a digital value including xe2x80x9caxe2x80x9d bits into an analog signal.
Such an apparatus generally includes a voltage divider chain in which each value that can be assumed by the digital value to be converted has an associated tap connected to the output connection of the apparatus via a selection switch.
Such an apparatus is shown by way of example in FIG. 1A. The apparatus shown is designed for converting a digital value including three bits into an analog signal.
The voltage divider chain: includes seven resistors R connected in series; has reference voltages REF-HI and REF-LO applied to the ends; and has taps A0 to A7.
The taps A0 to A7 are the starting points for lines L0 to L7, which are connected to an output connection OUT of the apparatus via selection switches S0 to S7.
The selection switches S0 to S7 are controlled by a decoder DEC on the basis of the digital value that will be converted. The decoder DEC has an input connection IN which is used to input the digital value that will be converted into an analog signal.
By way of example, the decoder DEC operates such that:
it closes the selection switch S0 and keeps all the other selection switches open when the digital value to be converted is 000;
it closes the selection switch S1 and keeps all the other selection switches open when the digital value to be converted is 001;
it closes the selection switch S2 and keeps all the other selection switches open when the digital value to be converted is 010;
it closes the selection switch S3 and keeps all the other selection switches open when the digital value to be converted is 011;
it closes the selection switch S4 and keeps all the other selection switches open when the digital value to be converted is 100;
it closes the selection switch S5 and keeps all the other selection switches open when the digital value to be converted is 101;
it closes the selection switch S6 and keeps all the other selection switches open when the digital value to be converted is 110; and
it closes the selection switch S7 and keeps all the other selection switches open when the digital value to be converted is 111.
As a result, the output connection OUT of the arrangement provides an analog voltage corresponding to the digital value.
FIG. 1B shows a symbol used later for the apparatus shown in FIG. 1A.
An apparatus of the type shown in FIG. 1A can also be in a form such that it converts the digital value into two analog signals that can be used as differential signals.
Such an apparatus is shown in FIG. 2A. The apparatus shown in FIG. 2A contains, like the apparatus shown in FIG. 1A, a voltage divider chain which: includes seven resistors R connected in series, has reference voltages REF-HI and REF-LO applied to the ends, and has taps A0 to A7.
The taps A0 to A7 are again the starting points for lines L0 to L7, which are connected to an output connection OUT1 of the apparatus via selection switches S0 to S7.
The taps A0 to A7 are also the starting points for lines L10 to L17, which are connected to a second output connection OUT2 of the apparatus via selection switches S10 to S17.
The selection switches S0 to S7 and S10 to S17 are controlled by a decoder DEC on the basis of the digital value that will be converted; the decoder DEC has an input connection IN which is used to input the digital value that will be converted into an analog signal.
In more precise terms, respectively one of the selection switches S0 to S7 and at the same time one of the selection switches S10 to S17 are closed, while all the other selection switches are respectively open.
As a result, the apparatus shown in FIG. 2A outputs two respective analog voltages. If the selection switches S0 to S7 and S10 to S17 are actuated such that the analog signal corresponding to the digital value which is to be converted is formed by subtracting the signal which is output from the output signal OUT2 from the signal which is output from the output connection OUT1 (or vice versa), this allows interference to be eliminated.
By way of example, the decoder DEC operates such that:
it closes the selection switches S0 and S10 and keeps all the other selection switches open when the digital value to be converted is 000;
that it closes the selection switches S2 and S11 and keeps all the other selection switches open when the digital value to be converted is 001;
that it closes the selection switches S4 and S12 and keeps all the other selection switches open when the digital value to be converted is 010;
that it closes the selection switches S6 and S13 and keeps all the other selection switches open when the digital value to be converted is 011;
that it closes the selection switches S7 and S13 and keeps all the other selection switches open when the digital value to be converted is 100;
that it closes the selection switches S7 and S12 and keeps all the other selection switches open when the digital value to be converted is 101;
that it closes the selection switches S7 and S11 and keeps all the other selection switches open when the digital value to be converted is 110; and
that it closes the selection switches S7 and S10 and keeps all the other selection switches open when the digital value to be converted is 111.
FIG. 2B shows a symbol used later for the apparatus shown in FIG. 2A.
If an apparatus as shown in FIG. 1A or as shown in FIG. 2A is part of an integrated circuit, the voltage divider chain is generally in the form of a long resistive track, i.e. without discrete resistive components. In this case, the resistive track and the taps are in a form and are arranged such that the resistive track between two adjacent taps has a respective electrical resistance which corresponds to the electrical resistance of one of the resistors R in the arrangements shown in FIGS. 1A and 2A.
An apparatus having a voltage divider chain implemented in this manner is shown in FIG. 3. The apparatus shown in FIG. 3 corresponds to the apparatus shown in FIG. 2A. Identical references denote components which are the same or which correspond to one another. The only difference between the apparatus shown in FIG. 3 and the apparatus shown in FIG. 2A is that the apparatus shown in FIG. 3 has no discrete resistors R. Instead, a resistive track RB is provided which, between adjacent taps, has a respective electrical resistance which corresponds to the electrical resistance of one of the resistors R in the arrangements shown in FIGS. 1A and 2A.
By omitting the lines S10 to S17, the selection switches S10 to S17 and the second output connection OUT2, an apparatus is obtained which corresponds to the apparatus shown in FIG. 1A.
For the sake of completeness, it will be noted that the resistive track RB is formed by a polylayer on the semiconductor chip containing the integrated circuit. Of the lines L0 to L7 and L10 to L17 coming from the taps A0 to A7, the first portion is likewise formed by a polylayer and the second portion is formed by a metal layer provided above the polylayer. The crossover for the lines from the polylayer into the metal layer, more precisely the plated-through hole provided for this purpose, is provided in order to connect these layers at a great distance from the taps A0 to A7 so that the plated-through hole cannot have any effect on the current flowing through the resistive track. In addition, it will be noted that no or just a very small current can flow through the lines L0 to L7 and L10 to L17, because this would affect the D/A conversion. This incidentally also applies to all other apparatus in which D/A conversion is carried out using voltage divider chains.
Implementing the voltage divider chain using a resistive track is relatively easy, but under some circumstances it gives rise to problems when integrating a D/A converter containing such a resistive track into an integrated circuit. This is particularly so when the D/A converter is intended to convert a digital value including a large number of bits into an analog signal. In this case, a very large number of taps need to be provided along the resistive track, which makes the resistive track very long. This results in the D/A converter having an unfavorable shape (long and narrow), which makes it difficult or in some cases even impossible to position the D/A converter on the semiconductor chip carrying the integrated circuit such that the chip area taken up by the integrated circuit is minimal.
To avoid this problem, the resistive track could be convoluted meandrously. An apparatus having a meandrously convoluted resistive track is illustrated in FIG. 4.
The arrangement shown in FIG. 4 largely corresponds to the arrangement shown in FIG. 3. The only difference is the shape of the resistive track RB.
The resistive track shown in FIG. 4 has vertically running sections RBV1 to RBV4 and horizontally running sections RBH1 to RBH3.
As can be seen from FIG. 4, the use of a meandrously convoluted resistive track RB allows the length/width ratio of the apparatus containing the resistive track to be varied as desired, which makes it possible to arrange such an apparatus on a semiconductor chip more easily and more efficiently.
However, a meandrously convoluted resistive track RB also has drawbacks.
One of these drawbacks is that the resistance of the resistive track RB is different at the corners, i.e. at the crossings between the vertically running sections RBV and the horizontally running sections RBH, than in the sections which run straight. Since the magnitude of this resistance varies greatly in practice, it is unavoidable that the resistance established between the taps connected to one another via a horizontal section RBH of the resistive track is different than between taps connected to one another via a vertical section RBV of the resistive track.
Another drawback of a meandrously convoluted resistive track RB is that the vertical sections RBV of the resistive track RB need to be a relatively great distance apart on account of the selection switches S0 to S7 and S10 to S17 which need to be provided between them, which means that the horizontal sections RBH of the resistive track need to be relatively long. The result of this is that the taps connected to one another via the horizontal sections RBH of the resistive track are connected to one another via a relatively long portion of the resistive track, and this in turn requires that the taps connected to one another via vertical sections RBV of the resistive track likewise need to be such a great distance apart. Otherwise, the taps would be distributed unevenly over the resistive track, which would result in nonlinear conversion of the digital value which is to be converted into an analog signal. The resultant large distances between the taps mean that an apparatus with a meandrously convoluted resistive track takes up more space than an apparatus with a resistive track running straight.
The problems cited could be overcome by running the horizontal sections RBH of the resistive track RB in a metal layer on the semiconductor chip containing the apparatus.
However, this would require acceptance of the drawback that the resistive track has contact points, more precisely plated-through holes for connecting the polylayer and the metal layer. These contact points have greatly varying resistances, which means that the resistances of the resistive track""s sections running between adjacent taps can vary, and can therefore likewise not ensure linear conversion of the digital value which is to be converted into an analog signal.
It is accordingly an object of the invention to provide an apparatus for converting an analog signal into a digital signal, which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide an apparatus for converting an analog signal into a digital signal that can be easily and efficiently accommodated on a semiconductor chip and that ensures a completely linear conversion of the digital value into an analog signal.
With the foregoing and other objects in view there is provided, in accordance with the invention, an apparatus for converting a digital value having a bits into an analog output signal. The apparatus including: 2b D/A converters, b being an integer greater than 0; and an output. For i=1 . . . 2b, a respective digital value having axe2x88x92b bits is supplied to an ith one of the D/A converters. Each ith one of the D/A converters is for converting the respective digital value having axe2x88x92b bits into an analog value. The respective digital value having axe2x88x92b bits corresponds to axe2x88x92b most significant bits in a sum of the digital value having a bits and a value xi. The value xi is selected to satisfy:                               ∑                      i            =            1                                2            b                          ⁢                  xe2x80x83                ⁢                  x          i                    =                        ∑                      i            =            1                                2            b                          ⁢                  (                      i            -            1                    )                      ,    ⁢      xe2x80x83  xe2x80x83and
xi=(ixe2x88x921)+n2b;
where n is an integer.
The output provides the analog output signal as a mean value obtained from the analog value from each one of the D/A converters.
In accordance with an added feature of the invention, xi is equal to ixe2x88x921.
In other words, the inventive apparatus is distinguished by the features listed below: The apparatus has 2b D/A converters. Here, b is an integer number which is greater than 0, and each of the D/A converters is designed to convert a digital value including axe2x88x92b bits. The digital value that is supplied (for i=1 . . . 2b) to the ith D/A converter for the purpose of D/A conversion corresponds to the axe2x88x92b most significant bits in the sum of the digital value that is to be converted by the apparatus and to a value xi. The values xi are selected such that they satisfy the conditions:                     ∑                  i          =          1                          2          b                    ⁢              xe2x80x83            ⁢              x        i              =                  ∑                  i          =          1                          2          b                    ⁢              xe2x80x83            ⁢              (                  i          -          1                )              ,xe2x80x83and
xi(ixe2x88x921)+n2b;
where n is any integer. The output signal from the apparatus is the mean value for the output signals from the D/A converters.
The fact that the D/A converters are designed for the purpose of D/A converting digital values including only xe2x80x9caxe2x88x92bxe2x80x9d bits, means that the voltage divider chain or the resistive track forming this chain in the D/A converters needs to have far fewer taps than is the case with a D/A converter which is designed for the purpose of D/A conversion of a digital value including xe2x80x9caxe2x80x9d bits. As a consequence of this, the voltage divider chain or the resistive track forming it can likewise be much shorter. This means that the apparatus can be given a shape which can be accommodated on a semiconductor chip more easily and more efficiently, even without meandrous convolution of the voltage divider chain or resistive track. Added to this is the fact that the shape can be varied as desired by altering the arrangement of the plurality of D/A converters and/or of the other apparatus components. This means that no meandrous convolution of the voltage divider chain or of the resistive track forming it and no acceptance of the associated problems and drawbacks is required in order to produce a simply designed and efficiently usable apparatus for converting a digital value into an analog signal, which apparatus also ensures a completely linear conversion of a digital value into an analog signal.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an apparatus for converting a digital value into an analog signal, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.